DV Positions: Define and implement IP/So C verification plans, build verification test benches to enable IP/sub-stem/So C level verification Develop functional tests based on verification test plan Drive Design Verification to closure based on defined verification metrics on test plan, functional and code coverage Debug, root-cause and resolve functional failures in the design, partnering with the Design team Qualifications and Skills : Bachelor's or Masters degree in Computer Science,



Electronics Engineering or equivalent practical experience 6/10+ of hands-on experience in Stem Verilog/UVM methodology and/or C/C++ based verification 6/ 10+ experience in IP/sub-stem and/or So C level verification based on Stem Verilog UVM/OVM based methodologies Experience in development of UVM based verification environments from scratch Experience in architecting and implementing Design Verification infrastructure and executing the full verification cycle Experience with verification of ARM/RISC-V based CPU sub-stems or So Cs Experience with IP or integration verification along with expertise of protocols like AMBA, PCIe, DDR, USB, Ethernet Experience in E tools and scripting (Python, TCL, Perl, Shell) used to build tools and flows for verification environments Experience with revision control stems like Mercurial(Hg), Git or SVN

📌 Senior Design Verification Engineer (Bengaluru)
🏢 Lu0026T Technology Services
📍 Bengaluru