Job Description

Memory Layout Engineer

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Location: Bengaluru

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Experience Required: 3+ Years

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Employment Type: Full-Time

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Job Summary:

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We are seeking an experienced and detail-oriented Memory Layout Engineer with 3+ years of hands-on experience in custom layout design and verification of memory IPs (SRAM, ROM, CAM, etc.). The ideal candidate will have a robust background in advanced technology nodes and be well-versed in layout tools and methodologies.

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Key Responsibilities:

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- Create and optimize transistor-level custom layouts for memory blocks (SRAM, ROM, eDRAM, CAM, etc.)
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- Work closely with circuit designers to ensure layout meets electrical and functional specifications.
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- Ensure designs meet DRC, LVS, ERC, and EM/IR requirements using industry-standard verification tools.
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- Perform parasitic extraction and assist in layout vs. schematic analysis and simulations.
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- Contribute to physical verification and sign-off processes.
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- Support tapeout activities and post-silicon validation as needed.
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- Collaborate with cross-functional teams across design, verification, and foundry interface.
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About Company

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ACL Digital, a leader in digital engineering and transformation, is part of the ALTEN Group. At ACL Digital, we empower organizations to thrive in an AI-first world. Our expertise spans the entire technology stack, seamlessly integrating AI and data-driven solutions from Chip to cloud. By choosing ACL Digital, you gain a strategic advantage in navigating the complexities of digital transformation. Let us be your trusted partner in shaping the future.

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📌 Memory Layout Engineer (Bengaluru)
🏢 ACL Digital
📍 Bengaluru