We have an opening for FPGA Design engineer role - Bangalore
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REQUIRED:
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EXP: 5 to 12 years
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- Experience with FPGA system design from IP Integration to implementation, Verilog RTL based IP design, Verilog/System Verilog based testbench development
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- Experience with AMD Vivado & Vitis SDK & VItis AI tools.
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- Experience with C/C++ in developing Embedded FW & scripting automation using Python
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- Experience with Petalinux build flow , familiarity with Uboot, linux driver changes and FPGA SoC debugging.
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