Job Description

STA Engineer

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KEY RESPONSIBILITIES:

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Responsible for Multi Voltage domain STA setting setup, execution and timing closure of GPU

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Drive the pre-route timing checks and QoR clean up to eliminate SDC issues and ensure a quality handoff for STA checks

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Ensuring timing correlation between PnR STA and timely feedbacks to PD team

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Generating block level HS session and using Top context from SoC for Block-SoC Interface timing closure.

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Generating timing ECO using Tweaker/Prime Closure.

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PREFERRED EXPERIENCE:

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3+ years of experience in timing closure of high frequency blocks like CPU/GPU (> GHz range)

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Analyzing the timing reports and identifying both design and constraints related issues.





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Worked on blocks with multiple power and voltage domains

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Preferred EDA tool experience: Primetime, Tweaker/Prime Closure, Innovus

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Solid Understanding of DFT modes requirements for timing signoff

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Positive understanding of physical design flow and ECO implementation

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Strong understanding of SDC constraints, OCV,AOCV,POCV analysis

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Strong TCL/scripting knowledge is mandatory.

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ACADEMIC CREDENTIALS:

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Bachelors or Masters degree in Electrical Engineering

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📌 Sta Engineer Bengaluru
🏢 MediaTek
📍 Bengaluru