Job Description
Job Summary:
nWe are seeking a highly accomplished Design for Testability (DFT) Engineer to join our elite team and lead the DFT efforts for our most critical ASIC and SoC projects. This senior-level position demands a mastery of DFT methodologies and the ability to drive the implementation of robust test strategies. You will play a pivotal role in ensuring the manufacturability and high-quality testing of our next-generation integrated circuits.
nResponsibilities:
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- Lead and define the overall DFT strategy for assigned projects, considering manufacturability, test coverage, and cost optimizationn
- Collaborate with design and verification teams throughout the design flow to seamlessly integrate DFT techniquesn
- Develop and implement advanced DFT methodologies (scan insertion, ATPG, Boundary Scan, Design for X) to achieve exceptional test coverage and fault detection ratesn
- Champion best practices for DFT and actively participate in design reviews, providing expert guidance on DFT feasibility and optimizationn
- Lead and mentor junior DFT engineers,



fostering a culture of excellence and knowledge sharing within the teamn
- Analyze test results, identify potential design issues, and recommend corrective actions to ensure high test qualityn
- Stay at the forefront of the DFT landscape by actively researching and adopting emerging tools and methodologiesn
- Manage and maintain DFT libraries and internal DFT standardsn
- Contribute to the continuous improvement of the DFT flow within the teamn

nQualifications:
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- Master's degree in Electrical Engineering, Computer Engineering, or a related field (highly preferred)n
- Minimum of 12 to 20 years of experience in Design for Testability (DFT) for complex ASICs and SoCsn
- Proven track record of successfully leading and implementing DFT strategies for high-volume productionn
- In-depth knowledge of advanced DFT concepts (scan insertion, ATPG, Boundary Scan, Design for Reliabil

📌 DFT Engineer (Kochi)
🏢 HCLTech
📍 Kochi