Job Description

Lead STA Engineer

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Among. The top 4 IT companies, in India ranked by market capitalization and revenue

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Bangalore /Hyderabad/Kochi

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Role Overview

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As a Lead STA Engineer(preferably 11+Yrs Experience ), you will be responsible for ensuring timing closure and sign-off for complex System-on-Chip/Subsystem designs. This involves analyzing, validating, and optimizing timing across multiple design hierarchies and technology nodes to meet performance, power, and reliability targets.

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Key Responsibilities

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Static Timing Analysis (STA):

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Perform STA at block and full-chip levels across multiple corners, modes, and conditions using industry-standard tools (e.g., Synopsys PrimeTime, Cadence Tempus).

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Timing Constraints Development:

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Create and validate SDC constraints for hierarchical SoC designs, including clocking, multi-mode, and multi-corner scenarios.

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Timing Closure:

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Drive timing closure during synthesis, place-and-route, and sign-off stages. Generate timing ECOs and collaborate with physical design teams for optimization.

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Cross-Functional Collaboration:

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Work closely with RTL, DFT, synthesis, verification, and physical design teams to resolve timing issues and ensure design quality.

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Automation & Scripting:

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Develop scripts (Tcl, Python, Perl) to automate STA flows, reporting, and constraint validation.

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Advanced Analysis:

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Handle OCV (On-Chip Variation), noise, crosstalk, and derate methodologies for accurate timing sign-off.

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Documentation & Reviews:

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Maintain STA methodology documents and participate in design reviews.

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Mentorship:

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Guide junior engineers on STA techniques and best practices.

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Required Skills & Tools

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Solid understanding of digital design principles, clocking, and timing concepts.

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Skills:

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Tempus

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Primetime

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SoC

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SDC

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MMMC

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ECO

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OCV

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Con tact

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Uday

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muday_bhaskar@yahoo .com

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Mulya Technologies

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"Mining the Knowledge Commun ity"

📌 STA Lead Engineer (Bengaluru)
🏢 Mulya Technologies
📍 Bengaluru