We are hiring Physical Design Engineer [EMIR, Innovus, FC, STA]

- Experience Required: 4 to10+ Years (Without training or internship)

- Location: Bangalore
- Your reference would be greatly appreciate

:

- Added adv experience in EMIR or STA.
- Responsible for floor-planning, timing constraints, physical synthesis, formal verification, clock tree optimization, routing, extraction, timing closure, DFT, signal integrity, physical verification and DFM.
- Execute block-level place and route assignments from Netlist through GDS flow.
- Perform full chip implementation of complex SoCs (RTL-to-GDSII) if needed.
- Close STA timing across all corners and modes for blocks and independently generate ECOs.
- Work with design teams to close CTS, IO timing, and DFT timing.
- Responsible for digital design automation, flow automation, and regression across RTL-to-GDSII.

Key Responsibilities

- Placement, routing, timing fixes

Required Skills & Expertise

- Innovus / ICC2/FC
- Basic PrimeTime
- Exposure to StarRC

Preferred Skills

- Solid TCL scripting capability
- Python scripting is a plus
- Experience in advanced nodes (7nm and below)

 Share your updated CV/resume to [email protected]

📌 Physical Design Engineers [PD] - STA - EMIR - Innovus - FC (Bengaluru)
🏢 SEMI LEAF
📍 Bengaluru