Job Description
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- Experience : 3 to 8 yearsn
- Location : Hyderabad/Noidan

n Role and Responsibilities:
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- Responsible for Memory Compiler layout development and verification.·n
- Responsible for Layout design and development of Memory blocks such as Array, Row/ Column decoder, sense amplifier, pre-charge, Control blocks for SRAM.·n
- Perform layout verification like LVS/ DRC/ Latchup, quality check and documentation.· Responsible for on-time delivery of block-level layouts with acceptable quality.· Demonstrate leadership Skill in planning, area/time estimation, scheduling, delegation and execution to meet project schedule/milestones in multiple project environment.·n
- Guide junior team-members in their execution of Sub block-level layouts & review their work.·n
- Contribute to effective project-management.·n
- Effectively communicate with engineering teams in the India & Korea teams to assure the success of the layout project.n

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n Qualification/ Requirements:
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- Should be well familiar with various levels of memory layouts from custom memory bits, leaf cells, control blocks, Read-Write, Sense Amplifiers, decoders.·n
- Should have expertise in floor planning, power planning, block area estimation of memory designs or compliers.·n
- Should be able to perform leaf cell layout development and physical verification.·n
- Should have adequate knowledge of schematics, interface with circuit designer and CAD and process development team.·n
- Valuable understanding of layout fundamentals i.e. Electro-migration, Latch-up, coupling, crosstalk, IR-drop, parasitic analysis, matching, shielding, etc.·n
- Understanding layout effects on the circuit such as speed, capacitance, power and area etc.,· Excellent in problem-solving skills in solving area, power, performance and physical verification of custom layout.·n
- Experience with Cadence tools including Virtuoso schematic editor Virtuoso layout L, XL & Verification tools like Mentor Calibre-

📌 Memory Layout Engineer (Noida)
🏢 ACL Digital
📍 Noida