Job Title: Lead Synthesis Engineer

Location: Bengaluru

Department: VLSI

Experience: 8–15 Years

Job Summary

We are seeking an experienced and highly motivated Lead Synthesis Engineer to lead a team of 5–8 engineers responsible for RTL-to-Gate synthesis, timing optimization, and design implementation support for advanced ASIC/So C projects. The ideal candidate will possess strong technical expertise in synthesis methodologies, timing closure, low-power design techniques, and team leadership. This role requires close collaboration with RTL, Physical Design, DFT, and STA teams to ensure high-quality silicon delivery within project schedules.

Key Responsibilities

Technical Leadership

Lead and mentor a team of 5–8 synthesis engineers, providing technical guidance, task allocation, and performance coaching.

Define and drive synthesis methodologies, best practices, and quality standards across projects.

Review synthesis strategies, constraints, reports, and deliverables to ensure consistency and quality.

Support project planning, effort estimation, and resource allocation.

Synthesis & Timing Closure

Perform RTL-to-Gate synthesis for complex ASIC/So C designs using industry-standard EDA tools.

Develop and maintain synthesis scripts, flows, and automation frameworks.

Analyze and optimize designs for timing, area, power, and congestion.

Collaborate with STA teams to achieve timing closure across multiple operating corners and modes.

Identify and resolve synthesis-related issues impacting downstream implementation.

Cross-Functional Collaboration

Work closely with RTL Design teams to improve code quality and synthesis efficiency.

Coordinate with Physical Design teams on floorplan-aware synthesis and implementation readiness.

Collaborate with DFT teams to ensure scan insertion and testability requirements are met.

Participate in design reviews and signoff discussions.

Process Improvement





Drive continuous improvements in synthesis methodologies, productivity, and automation.

Develop and maintain documentation, guidelines, and training materials.

Evaluate and deploy new tool features and synthesis techniques to improve design quality.

Required Qualifications

Bachelor's or Master's degree in Electronics Engineering, Electrical Engineering, Computer Engineering, or related field.

8+ years of experience in ASIC/So C synthesis and timing closure.

Strong expertise in RTL synthesis, timing constraints development, and optimization techniques.

Hands-on experience with synthesis tools such as:

Synopsys Design Compiler (DC/DCG)

Cadence Genus

Robust understanding of

Static Timing Analysis (STA)

Low-power design methodologies (UPF/CPF)

DFT concepts and scan integration

Physical-aware synthesis

ASIC design flow from RTL to GDSII

Experience with scripting languages such as Tcl, Perl, Python, or Shell.

Leadership Skills

Proven experience leading and mentoring engineering teams of 5–8 members.

Strong project management, planning, and execution skills.

Excellent problem-solving and debugging capabilities.

Effective communication and stakeholder management skills.

Preferred Qualifications

Experience with advanced technology nodes (7nm, 5nm, 3nm, or below).

Knowledge of MCMM timing methodologies.

Experience in high-performance, low-power So C development.

Familiarity with formal verification and equivalence checking tools.

Success Metrics

Achievement of synthesis quality targets (Qo R) for timing, power, and area.

On-time delivery of synthesis milestones and project commitments.

Team productivity, technical growth, and successful execution of multiple concurrent projects.

Continuous improvement in methodology efficiency and automation.

Direct Reports: 5–8 Synthesis Engineers

This position offers an opportunity to lead a talented engineering team and drive the successful implementation of next-generation semiconductor products.

📌 Lead Synthesis Engineer (Bengaluru)
🏢 Leadsoc Technologies
📍 Bengaluru