Job Description
Analog Layout Engineer
nLocation: Bengaluru, India
nExperience: 5–10 Years
nRole
nDesign and implement high-performance Analog/Mixed-Signal layouts for advanced-node SoCs. Own layout execution from device level to tapeout while delivering optimal matching, reliability, manufacturability, and first-pass silicon success.
nWhat You'll Do
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- Develop full-custom Analog Layouts for high-performance IPs including PLL, LDO, Bandgap, ADC, DAC, SerDes, DDR PHY, PMIC, Data Converters, IOs, and Clocking Circuits.n
- Perform device placement, routing, floorplanning, shielding, guard ring implementation, common-centroid matching, interdigitation, and parasitic-aware optimization.n
- Drive layout closure for DRC, LVS, ERC, Antenna, DFM, Density, EM/IR, PERC, and Reliability.n
- Optimize layouts for matching, noise isolation, IR drop, electromigration, yield, and performance.n
- Collaborate with Circuit Design, Reliability, Physical Verification, and Process teams to achieve PPA and silicon targets.n




- Support layout migration across technology nodes and contribute to layout methodology, automation, and best practices.n

nWhat You Bring
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- 5–10 years of hands-on experience in Analog Full Custom Layout.n
- Robust expertise in device matching, common centroid, interdigitation, shielding, guard rings, deep N-Well, substrate isolation, and analog routing techniques.n
- Experience with Analog IPs such as PLL, LDO, Bandgap, ADC/DAC, SerDes, DDR PHY, PMIC, USB, PCIe, MIPI, or High-Speed IOs.n
- Hands-on experience with Cadence Virtuoso XL/Studio, Calibre/PVS/ICV, and extraction tools such as Quantus or StarRC.n
- Strong understanding of DRC/LVS/ERC, DFM, Antenna, EM/IR, PERC, and advanced-node layout challenges.n
- Experience with FinFET technologies (16nm/7nm/5nm/3nm) and physical signoff methodologies.n
- Scripting experience using SKILL, Tcl, or Python is an added advantage.n

nPreferred
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- Experience in Memory Layout, High-Speed

📌 Analog Layout Engineer (Bengaluru)
🏢 Leadsoc Technologies
📍 Bengaluru