We are hiring for one of our reputed clients for the following position. If you're interested and your experience matches the requirement, we'd love to hear from you.
Position:Hardware Design Engineer 3
Experience: 6-9 Years
Location: New delhi
Contract:12 Months
Role & responsibilities
- Strong understanding of Siemens Tessent ATPG tools and SSN methodology.
- Hands-on experience in ICL, PDL, Stuck-at and Transition fault pattern generation.
- Good understanding of scan coverage and experience in coverage analysis.
- Experience with timing and non-timing gate-level simulations and debugging simulation failures.
- Experience performing DFT DRC checks at RTL and analyzing violations.
- Strong knowledge of Scan structures, IEEE 1149.1, IEEE 1687, ATPG methodology and DFT flow.
- Good understanding of timing constraints, synthesis flow and scan insertion using Design Compiler (DC) / Fusion Compiler (FC).
- Robust TCL/Scripting skills.
📌 Hardware Design Engineer 2314 (New Delhi)
🏢 Sunrise BizTech Systems
📍 New Delhi
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