Experience 3–8 years

Job Summary

Looking for a DFT Engineer with hands-on experience in DFT implementation, scan insertion, ATPG, scan compression, coverage analysis, and DFT verification for ASIC/SoC designs.

Key Responsibilities

- Develop and implement DFT architecture for ASIC/SoC designs.
- Perform scan insertion, scan stitching, scan compression, and DFT DRC.
- Generate and debug ATPG patterns for stuck-at and transition faults.
- Analyze and improve fault coverage and debug untestable/aborted faults.
- Work on MBIST/LBIST, JTAG/Boundary Scan as required.
- Perform DFT verification at RTL and gate level.
- Define and debug test-mode and scan timing constraints.
- Collaborate with RTL, Synthesis, STA, Physical Design, and Verification teams.




- Support DFT sign-off and tape-out activities.
- Automate DFT flows using Tcl/Python/Perl/Shell.

Required Skills
- Solid knowledge of ASIC DFT and scan methodology.
- Experience with ATPG, scan compression, DFT DRC, and fault coverage.
- Knowledge of MBIST, LBIST, JTAG, and Boundary Scan is a plus.
- Proficiency in Verilog/SystemVerilog and Linux.
- Experience with tools such as Synopsys TestMAX/TetraMAX, Cadence Modus, or Siemens Tessent.

Education B.E./B.Tech/M.E./M.Tech in **

📌 DFT Engineer (Bengaluru)
🏢 Mirafra Technologies
📍 Bengaluru