Tips: Provide a summary of the role, what success in the position looks like, and how this role fits into the organization overall.
Responsibilities
- Able to independently work on IC layouts of high performance analog blocks (such as ADC, DAC, PLL, and SERDES, for example)
- Could be able mitigate all Layout dependent effects and produce high performance and high quality IC layouts including physical verification checks DRC, LVS, DFM, ERC, EM, IR etc.
- Automation using SKILL/PERL/Python is a plus
- Self starter with the ability to define and adhere to schedule and methodology
- Must possess robust social skill and be an excellent team mate
Qualifications
BE / Btech Electronics and Communication
📌 AMS, RF, Memory, Standard Cell Layout Engineer with 4 to 8 years of experience in 90nm, 65nm, 40nm, 7nm, 6nm, 5nm & 3nm technology nodes (Bengaluru)
🏢 CoreIC Technologies
📍 Bengaluru
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