Job DescriptionLead STA Engineer
n Among. The top 4 IT companies, in India ranked by market capitalization and revenue
nBangalore /Hyderabad/Kochi
nRole Overview
nAs a Lead STA Engineer(preferably 11+Yrs Experience ), you will be responsible for ensuring timing closure and sign-off for complex System-on-Chip/Subsystem designs. This involves analyzing, validating, and optimizing timing across multiple design hierarchies and technology nodes to meet performance, power, and reliability targets.
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nKey Responsibilities
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nStatic Timing Analysis (STA):
nPerform STA at block and full-chip levels across multiple corners, modes, and conditions using industry-standard tools (e.g., Synopsys PrimeTime, Cadence Tempus).
nTiming Constraints Development:
nCreate and validate SDC constraints for hierarchical SoC designs, including clocking, multi-mode, and multi-corner scenarios.
nTiming Closure:
nDrive timing closure during synthesis, place-and-route, and sign-off stages. Generate timing ECOs and collaborate with physical design teams for optimization.




nCross-Functional Collaboration:
nWork closely with RTL, DFT, synthesis, verification, and physical design teams to resolve timing issues and ensure design quality.
nAutomation & Scripting:
nDevelop scripts (Tcl, Python, Perl) to automate STA flows, reporting, and constraint validation.
nAdvanced Analysis:
nHandle OCV (On-Chip Variation), noise, crosstalk, and derate methodologies for accurate timing sign-off.
nDocumentation & Reviews:
nMaintain STA methodology documents and participate in design reviews.
nMentorship:
nGuide junior engineers on STA techniques and best practices.
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nRequired Skills & Tools
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nStrong understanding of digital design principles, clocking, and timing concepts.
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nSkills:
nTempus
nPrimetime
nSoC
nSDC
nMMMC
nECO
nOCV
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n Con tact
nUday
nmuday_bhaskar@yahoo .com
n Mulya Technologies
n"Mining the Knowledge Commun ity"

📌 STA Lead Engineer (Bengaluru)
🏢 Mulya Technologies
📍 Bengaluru