Job Description
Job Description:
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- Responsible for chip level STA convergence from early stages to signoff.n
- Participate in top level floor plan and clock planning.n
- IP & SoC timing constraints definition for all modes including DFTn
- Constraints quality checkn
- Multimode-multi corner timing analysis.n
- Timing ECO generation.n
- Block and SoC level timing convergence.n
- Block and SoC level Synthesis.n
- Block and SoC level equivalence check.n

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nExperience Required:
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- 5 to 8 years of experience in SOC level timing convergencen
- Synthesis and equivalence checkn
- Solid timing conceptsn
- Working knowledge of low power design involving multiple power domains.n
- Proficiency in scripting languages such as TCL, Perl, or Python for automation.n
- Familiarity with industry-standard EDA tools for STA like Tempus and PrimeTimen
- Exposure to complex design having multiple asynchronous clocks.n

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📌 STA Engineer (Bengaluru Urban)
🏢 HrdWyr
📍 Bengaluru Urban