Senior Physical Design Engineer – VLSI
LeadIC Design Pvt Ltd is looking for a Senior Physical Design Engineer with strong hands-on expertise in RTL-to-GDSII implementation, P&R;, CTS, STA, timing closure, and PPA optimization.
What You’ll Do
Own physical design implementation from netlist to GDSII.
Drive floorplanning, power planning, placement, CTS, routing, optimization, and signoff.
Perform STA and timing closure for setup/hold violations.
Debug and optimize timing, congestion, transition, capacitance, and fanout issues.
Drive PPA optimization across performance, power, and area.
Support IR drop, EM, signal integrity, antenna, DRC/LVS, and physical signoff.
Execute ECOs and implementation fixes through final closure.
Work closely with RTL, STA, DFT, verification, and other design teams.
Improve physical design flows, methodologies, scripts, and automation.
Mentor engineers and take ownership of critical implementation challenges.
What We’re Looking For




Strong hands-on experience in VLSI Physical Design / ASIC Physical Implementation.
Expertise in Floorplan → Placement → CTS → Routing → Timing Closure → GDSII.
Experience with Synopsys, Cadence, or Siemens EDA tools.
Knowledge of DRC, LVS, IR/EM, SI/noise, antenna, and signoff.
Experience with advanced-node SoC/IP designs is a plus.
Strong digital design and semiconductor fundamentals.
Excellent problem-solving and debugging skills.
Bachelor’s/Master’s degree in EE/ECE/VLSI/Microelectronics or related field.
Why Join LeadIC?
Work on challenging SoC/IP physical implementation, solve real timing and PPA problems, and take robust technical ownership across the RTL-to-GDSII flow.
If Physical Design, Timing Closure, and PPA optimization are your strengths, we want to hear from you.

📌 Senior Physical Design Engineer (Bengaluru)
🏢 leadIC Design
📍 Bengaluru