Job Description:
Responsible for chip level STA convergence from early stages to signoff. Participate in top level floor plan and clock planning. IP & So C timing constraints definition for all modes including DFT Constraints quality check Multimode-multi corner timing analysis. Timing ECO generation. Block and So C level timing convergence. Block and So C level Synthesis. Block and So C level equivalence check.
Experience Required:
5 to 8 years of experience in SOC level timing convergence Synthesis and equivalence check Robust timing concepts Working knowledge of low power design involving multiple power domains. Proficiency in scripting languages such as TCL, Perl, or Python for automation. Familiarity with industry-standard EDA tools for STA like Tempus and Prime Time Exposure to complex design having multiple asynchronous clocks.
📌 Sta Engineer (Bengaluru)
🏢 HrdWyr
📍 Bengaluru
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