Location: Bangalore, India |Company: LTSCT — L& T Semiconductor Technologies Limited
Reporting To: Senior Architect, DC HW Systems | Experience: 10+ years (mandatory)
Role Summary
We are hiring two AIML Pipeline / Dataflow Design Leads to implement the BFOS-MPE (Broadcast-Fed Output-Stationary Matrix Processing Engine) — the compute heart of x PU. You will own the compute datapath, the broadcast network, PE array control, sparsity engines (SWS), and dual-mode (matrix + GPU) switching. You will also own the LLVM interface to the x PU.
Key Responsibilities Own micro-architecture and RTL of the BFOS-MPE compute datapath — dual 256×256 PE arrays (65,536 PEs each) operating at 2 GHz. Design the broadcast-fed input network and output-stationary accumulation scheme that define the BFOS dataflow. Implement PE array control, sequencing, and the sparsity engine (SWS) for structured/unstructured sparsity acceleration. Architect dual-mode operation enabling switching between dense matrix (GEMM/convolution) and GPU-style workloads.
Drive numerical formats and precision (FP/BF/INT, mixed precision) and validate functional correctness against reference models. Coordinate and integrate contributions into the dataflow codebase and verification plan. Own performance/utilization modeling, power-efficiency optimization, and PPA closure for the compute engine. Own the ISA/FW routines for the optimal utilization of the HW compute structures in the x PU; as part of the LLVM development.
Required Skills & Experience 10+ years in compute datapath, DSP, GPU, or AI-accelerator micro-architecture and RTL design. Deep understanding of systolic/spatial arrays, matrix-multiply dataflows (output/weight/row-stationary), and broadcast networks. Robust expertise in RTL (System Verilog) for high-throughput arithmetic datapaths and control. Solid grounding in numerical formats and arithmetic (FP32/BF16/FP8/INT8), mixed-precision, and rounding/accuracy trade-off