Job Title: Synthesis Engineer
Experience: 3+ Years
Domain: VLSI / ASIC Design
Job Summary:
We are looking for a skilled Synthesis Engineer with 3+ years of experience in RTL-to-Gate synthesis and timing optimization. The candidate will be responsible for achieving timing, area, and power targets while ensuring high-quality netlist generation for downstream Physical Design.
Key Responsibilities:
- Perform RTL-to-Gate synthesis and netlist generation
- Apply and validate SDC timing constraints
- Drive timing, area, and power optimization
- Work on multi-mode multi-corner (MMMC/MCMM) synthesis flows
- Analyze and fix synthesis-related timing violations
- Collaborate with RTL, DFT, and Physical Design teams
- Support LEC (Logical Equivalence Check) and gate-level simulations
- Debug synthesis and constraint-related issues
Required Skills:




- Hands-on experience with Synopsys Design Compiler
- Experience with Cadence Genus (added advantage)
- Robust knowledge of SDC, timing constraints, and STA concepts
- Understanding of low-power techniques (UPF/CPF)
- Familiarity with technology libraries and timing models
- Proficiency in TCL scripting
- Good debugging and analytical skills
Preferred Qualifications:
- Experience in advanced technology nodes (7nm / 14nm / 28nm)
- Knowledge of DFT and scan insertion concepts
- Exposure to Physical Design flow
Education:
- B. E / B. Tech in ECE / EEE
- M. Tech / MS in VLSI / Microelectronics (Preferred)

📌 Synthesis engineer (Bengaluru)
🏢 Leadsoc Technologies
📍 Bengaluru