Design verification engineer (Hyderabad)

Design verification engineer (Hyderabad)

01 Sep
|
ACL Digital
|
Hyderabad

01 Sep

ACL Digital

Hyderabad

Experience: 2-3 Years
Location: Hyderabad
Education: B. E./B. Tech. in ECE/EEE
Roles and Responsibilities
1. Robust expertise in UVM-based verification.
2. Hands-on IP-level verification exposure and a solid understanding of serial protocols are a must.
Share resumes at raksha.k@

📌 Design verification engineer (Hyderabad)
🏢 ACL Digital
📍 Hyderabad

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