This position is listed on behalf of a partner company, who manages all applications and next steps. Our partner is looking for a Staff Engineer - Design Verification based in India.

This is a senior technical leadership opportunity focused on verifying next-generation high-speed interconnect IP and SoC technologies. You will define verification strategy and architecture for complex protocols including PCIe, CXL, Ethernet, and UCIe. The role combines deep hands-on engineering with technical leadership, from building reusable UVM environments to driving coverage closure and silicon-level debug. You will work closely with design, architecture, and validation teams in a highly team-oriented, globally distributed engineering environment. The position offers the opportunity to influence verification methodologies across sophisticated chiplet, AI, and high-performance computing architectures. You will also mentor engineers and establish verification practices that can scale across multiple projects and tape-outs.



This is an ideal role for an experienced verification expert who wants meaningful ownership over challenging semiconductor designs.

Accountabilities
- Define and lead scalable verification strategies and plans for complex PCIe, CXL, Ethernet, and UCIe subsystems.
- Architect and develop layered, reusable UVM agents, environments, testbenches, and verification components for high-speed protocol verification.
- Drive verification of advanced standards including PCIe Gen5/Gen6, CXL 3.x, Ethernet 200G/400G, and UCIe PHY and Adapter layers.
- Establish coverage-driven verification strategies and lead functional coverage closure, assertion-based verification, SVA, and metric-driven sign-off.
- Lead complex debugging and root-cause analysis across simulation, emulation, prototyping, and silicon bring-up environments.
- Collaborate closely with design, architecture, and validation teams to identify risks, resolve issues, and deliver robust IP and SoC implementations.
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📌 Staff Engineer (India)
🏢 Jobgether
📍 India