Job DescriptionBrief About Tech Mahindra – Silicon Engineering NTech Mahindra Silicon Engineering is a key part of Tech Mahindra's semiconductor and engineering services portfolio, delivering end-to-end solutions across the silicon lifecycle for global semiconductor, automotive, consumer, and industrial clients. The practice focuses on VLSI, embedded systems, and platform engineering, supporting customers from architecture and design through verification, validation, and sustenance engineering. NnThe SiliconEngineering unit works across IP, Subsystem, and SoC-level development, offering capabilities in areas such as Design Verification, RTL Design, DFT, Physical Design, Memory Design, Custom Layout, Post-Silicon Validation, Embedded Software, and System Modeling & Simulation. Teams leverage industry-standard methodologies, tools, and design frameworks to deliver high-quality, production-ready silicon solutions. NnBacked by Tech Mahindra's global engineering DNA, the Silicon Engineering practice collaborates with leading semiconductor and technology clients worldwide, operating as an extended engineering arm to accelerate innovation, reduce time-to-market, and ensure reliable, scalable silicon platforms. It is part of Tech Mahindra's broader engineering-led growth strategy serving multiple global industries. NnAbout the Role NWe are looking for an experienced Memory Layout Engineer to join our advanced silicon design team. In this role, you will be responsible for the physical layout development of high-density memory IPs including SRAM, Register Files, ROM, Compiler Memories, and Custom Memory Arrays across advanced technology nodes. NnThe ideal candidate should possess strong hands-on expertise in memory layout implementation and verification for TSMC 2nm, 3nm, 5nm technologies or Samsung advanced nodes including 3nm, 4nm, and below. You will collaborate closely with Circuit Design, Memory Design, Process, Verification, and Foundry teams to deliver highly optimized memory layouts meeting stringent power, performance, area, manufacturability,



and reliability requirements. NnKeyResponsibilities Nn Develop and implement full-custom layouts for SRAM, Register Files, ROM, Memory Compilers, and Memory Macros. N Design highly optimizedlayouts meeting Power, Performance, Area (PPA), Yield, and Reliability requirements. N Perform custom layout design for memory bit-cells, peripheral circuits, sense amplifiers, decoders, and control logic. N Execute layout implementation for advanced process nodes including: N TSMC 2nm, 3nm, 5nm or Samsung 3nm, 4nm and advanced FinFET/GAA technologies N Ensure layout compliance with foundry design rules, matching requirements, and reliability guidelines. N Perform layout verification using: DRC, LVS, ERC, PEX, Antenna Checks N Optimize layouts for area reduction, matching, parasitics, and manufacturability. N Work closely with circuit designers to resolve performance and layout challenges. N Analyze extraction results and support post-layout simulations. N Drive physical verification closure and tape-out readiness. N Collaborate with process technology and foundry teams to implement node-specific best practices. N Develop automation scripts and methodologies to improve layout productivity. N Participate in technical reviews, design audits, and customer discussions. NnnQualification NBE/BTech/ME/MTech degree in Electronics, Electrical Engineering, VLSI, Microelectronics, or related disciplines. NRequired Skills Nn Strong experiencein Memory Layout. N Hands-on experience with: SRAM Layout, Register File Layout, Memory Compiler Layout, ROM Layout, High-Density Memory Arrays N Expertise in TSMC 5nm, 3nm,



2nm technologies or with experience with Samsung 4nm, 3nm and advanced process nodes. N Robust knowledge of: FinFET Technologies, Gate-All-Around (GAA) Technology, Multi-Patterning Requirements, Advanced Design Rules N Proficiency in layout tools such as: Cadence Virtuoso, Cadence Layout XL, Synopsys Custom Compiler N Experience with physical verification tools: Calibre DRC, Calibre LVS, Calibre PEX N Understanding of electromigration (EM), IR drop, reliability, and yield optimization. N Strong understanding ofsemiconductor manufacturing processes. N Experience in parasiticextraction and post-layout analysis. N Proficiency in scripting languages such as SKILL, Tcl, Perl, Python, or Shell. N Excellent debugging andproblem-solving skills. NnnPreferred Skills Nn Experience with advanced-node memory products for AI, HPC, Mobile, Automotive, and Networking applications. N Knowledge of SRAM bit-cell architecture and characterization. N Experience in technology migration across multiple foundries. N Exposure to custom analog layout concepts and matching techniques. N Experience with low-power memory design methodologies. N Familiarity with foundry signoff requirements and tapeout processes. N Experience supporting silicon bring-up and failure analysis activities. N Understanding of reliability checks including: ESD, Latch-up, EMIR Analysis, Aging Effects NnnTechnology Node Experience (Mandatory) NTSMC Nodes Nn N5 / N5P (5nm) N N3 / N3E (3nm)n N2 (2nm) NnSamsung Nodes Nn SF4 (4nm)n SF3 (3nm GAA) N Advanced FinFET & GAA Technologies NnnExperience Range: 4-8 Years NnWhyJoin Tech Mahindra Silicon Engineering? NJoin a world-class semiconductor engineering team working on next-generation memory technologies for leading global semiconductor companies. This role provides an opportunity to contribute to cutting-edge SRAM and advanced memory IP development on TSMC 2nm/3nm/5nm and Samsung 3nm/4nm technologies, enabling the future of AI, HPC, Mobile, Automotive, and Data Center platforms.

📌 Memory Layout (Vasanthanagar)
🏢 Tech Mahindra
📍 Vasanthanagar