Job DescriptionSenior LEC/CLP Engineer NnExperience:- 3 to 6 Years NNotice Period:- 0 to 45 Days NLocation:- Bangalore NnRole Overview: NnWe are seeking a experienced LEC / CLP Engineer with expertise in Logic Equivalence Check (LEC) and Conformal Low Power (CLP) methodologies. NnKeyResponsibilities: Nn Lead Logic Equivalence Check (LEC) and Low Power verification (CLP) activities across block and full-chip levels. Nnnn Define and implement LEC/CLP methodologies using industry-standard tools (Cadence Conformal, Synopsys Formality, etc.). Nnnn Validate low-power architecture, UPF/CPF constraints, and intent across multiple domains. Nnnn Collaborate with RTL, Synthesis, and Physical Design teams to resolve mismatches. Nnnn Review and debug LEC/CLP failures to drive sign-off closure. Nnnn Automate verification flows using Python/Perl/TCL scripting.



Nnn NRequired Skills NnExpertise with tools like Cadence Conformal, Synopsys Formality, or equivalent. Nn Solid understanding of RTL-to-netlist equivalence, low-power UPF/CPF verification, and multi-power domain SoCs. N Proven track record in debugging LEC/CLP failures and collaborating across design teams. N Proficiency in scripting (Python, Perl, TCL) for automation. N Strong analytical, problem-solving Nnn NPreferred Qualifications: Nn Master’s or Bachelor’s in Electronics / Electrical / VLSI Engineering. N Experience in advanced nodes (7nm and below). N Exposure to low-power design methodologies and complex SoC projects. Nn

📌 Senior Lec / Clp Engineer (Vasanthanagar)
🏢 Leadsoc Technologies
📍 Vasanthanagar