Job DescriptionStatic Timing Analysis (STA) Lead NnJoin the India team of most cutting-edge and well-funded storage startup in Silicon Valley as the Lead STA Engineer working on timing closure of complex high performance ASIC in latest technology nodes. N nAs a STA lead you willbe working on PrimeTime based flow development and timing closure of multi-million gate SoC design for all modes and all corners in 16/12/7/5nm processes. NnLocation: Bangalore, KA. India N nQualification and Skillset Requirements N n N Minimum BE/BS degree (Masters preferred) in Electrical/Electronics Engineering/VLSI N 10+ years of practical experience in Static Timing Analysis (STA) using Primetime N Robust fundamentals in digital ASIC design N Understanding of SoC design and implementation methodology and challenges N Understanding of one ormore of design flows like Synthesis, Constraint development and STA (Functional and DFT modes)



and Physical Design N Good hands on expertisewith industry standard implementation tools like – Synopsys PrimeTime, Design Compiler/Fusion Compiler etc. for block as well as top level N Able to work with TCL and Perl scripting and flow automation N Excellent communicationand team work NnnRoles And Responsibilities N n N Work on STA methodologyand flow development N Develop and integrate constraints at block and SoC level N Provide early feedback on design/timing issues and solutions N Work with Backend team for timing closure during PnR N Work with IP and SoC Design team in optimizing the design to meet timing N Work on timing closure for block/top, all modes/corners by providing timing ECOs etc. Nn

📌 Static Timing Analysis (Sta) Lead (Vasanthanagar)
🏢 ScaleFlux
📍 Vasanthanagar