Technical Lead - Design Verification
Experience: 8+ Years Location: Bengaluru
We are seeking a highly skilled and experienced
Senior Design Verification Engineer
to join our SoC/ASIC verification team in Bangalore. The ideal candidate will have a deep understanding of the verification lifecycle, from test planning to coverage closure, and be able to independently drive complex verification tasks for IP, subsystem, or full-chip level designs.
Key Responsibilities: Develop and execute
test plans
for IP/subsystem/full-chip level verification. Build and maintain
constrained-random
and
directed testbenches
using System Verilog and UVM. Drive
functional coverage
closure and ensure high-quality tape-outs. Collaborate with RTL designers, architecture, and software teams to understand design features and define test scenarios. Participate in
code reviews , debug RTL/testbench issues, and file bug reports. Use industry-standard tools like
VCS, Questa Sim, Verdi, Synopsys, Cadence, or Mentor
toolchains.



Mentor junior team members and lead small verification teams or projects when required. Support post-silicon validation teams and participate in bring-up/debug if necessary.
Required Skills and Qualifications: B.E/B. Tech or M.E/M. Tech in Electronics, Electrical, or related field. 8+ years
of experience in ASIC/SoC design verification. Solid expertise in
System Verilog ,
UVM , and
object-oriented programming . Proven track record in building and maintaining verification environments from scratch. Experience in
assertion-based verification ,
coverage analysis , and
debug tools . Solid understanding of
digital design concepts ,
SoC architecture , and
protocols
like AMBA (AXI, AHB), PCIe, USB, or DDR. Hands-on experience with
simulation tools ,
waveform viewers , and
version control systems (Git, Perforce, etc.) . Excellent problem-solving, communication, and team collaboration skills.

📌 Staff Engineer (India)
🏢 ACL Digital
📍 India