Roles & Responsibilities

- Develop and implement RTL designs for security cores and security subsystems using Verilog/SystemVerilog.
- Participate in ASIC/SoC design and development from RTL through implementation and sign-off stages.
- Perform and debug RTL Lint, CDC, LEC and low-power checks.
- Analyze and resolve design issues identified during ASIC development and sign-off flows.
- Collaborate with Design, Verification, DFT, Physical Design and other cross-functional teams to ensure design quality and project milestones.
- Contribute to design reviews, code reviews and technical documentation.
- Track project status and communicate progress, risks and issues to the project/team leads.
- Follow established ASIC design methodologies, coding guidelines and database/version-control flows.
- Support continuous improvement and automation of design processes using Python/Perl/C/C++, where applicable.

RTL Design | ASIC | SoC | Verilog | SystemVerilog | Lint | CDC | LEC | Low Power | Security Subsystem | Python | C/C++

📌 Rtl Design Engineer (Bangalore Rural)
🏢 Agile Ventures
📍 Bangalore Rural