Job Summary
We are looking for a skilled Physical Design Engineer to support end-to-end ASIC/SoC implementation from netlist/RTL to GDSII . The engineer will be responsible for physical implementation, timing closure, PPA optimization, physical verification, and sign-off while working closely with RTL, synthesis, STA, DFT, and verification teams.
Key Responsibilities
Execute the complete physical design flow:
Floorplanning
Power planning
Placement
Clock Tree Synthesis (CTS)
Routing
Optimization
ECO implementation
Physical sign-off
Perform Static Timing Analysis (STA) and resolve setup, hold, transition, and clock violations.
Analyze and optimize timing, power, area, congestion, and signal integrity .
Work on MMMC (Multi-Mode Multi-Corner) implementation and timing closure.
Develop and review timing constraints, including SDC, clocks, generated clocks, and timing exceptions .
Perform physical verification and sign-off activities including DRC, LVS, antenna, EM/IR, and power integrity checks.
Debug placement, routing, congestion, timing, and physical-design violations.
Collaborate with RTL, synthesis, STA, DFT, power, and verification teams to achieve project milestones.




Support tape-out activities and ensure design quality meets performance, power, area, and reliability targets.
Develop and improve implementation flows using Tcl/Python/Perl/Shell scripting .
Participate in methodology development and automation initiatives.
Required Technical Skills
Strong understanding of ASIC/VLSI Physical Design flow from RTL/Netlist to GDSII .
Valuable knowledge of:
Floorplanning
Placement
CTS
Routing
Timing closure
ECO
Physical verification
Power planning
Strong understanding of setup/hold timing and STA .
Knowledge of MMMC analysis and timing constraints .
Experience with industry-standard EDA tools such as:
Cadence Innovus
Synopsys ICC2/Fusion Compiler
Synopsys PrimeTime
Cadence Tempus
Calibre/ICV
Scripting knowledge in Tcl, Python, Perl, or Shell .
Understanding of DRC, LVS, EM/IR and power integrity is preferred.
Exposure to low-power design/UPF and advanced technology nodes is an advantage.
Education
B.E./B.Tech/M.E./M.Tech in Electrical Engineering, Electronics & Communication, VLSI, Microelectronics, or a related field .
Experience
3–6 years: Physical Design Engineer

📌 PD Engineer-Noida (Sector 27)
🏢 Mirafra Technologies
📍 Sector 27