Roles & Responsibilities

- Implement contemporary DFT solutions for leading edge ICs on latest technology nodes, including implement the DFT architecture.
- Work with RTL, custom digital/analog, verification, physical implementation, and timing teams during this DFT implementation.
- Set-up, run, and debug block-level, SOC-level as well as full-chip ATPG (Automatic Test Pattern Generation) runs.
- Deliver bring-up of test patterns and features post tape-out.
- Manage DFT design flow infrastructure to lead to a successful DFT implementation.
- Provide adapt off-the-shelf capabilities to build necessary CAD solutions.
- Develop test automation solutions for Design-for-Test (DFT) insertion and verification.
- Perform CAD development of the design methodology of memory build in self-test (MBIST).
- Build the DFT implementation flow infrastructure, coordinate and support its deployment.

Key Qualifications





- Bachelor's or foreign equivalent degree in Electrical Engineering, Computer Engineering, or a related field and five (5) years of experience in the job offered or related occupation.
- Experience must include five (5) years involved in: DFT architecture and planning for complex multi-million gate SoCs in latest technology nodes; SCAN/ATPG, and MBIST for complex multi-million gate SoCs; Mentor Tessent tool flows and Synopsys DFT compiler flows; creating and maintaining the EDA tool flows using PERL/Shell scripting; Silicon bring-up experience of MBIST and SCAN; creating iJTAG structure in Verilog; Logic Synthesis and Static Timing Closure.

Experience
5 to 8 Years
Education
BE/ ME/ B.Tech/ M.Tech/ MS
Location
San Jose, CA, USA

📌 Sr. DFT Engineer (VRS Nagar)
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📍 VRS Nagar