RTL Design Engineer (Hyderabad)

RTL Design Engineer (Hyderabad)

02 Sep
|
ACL Digital
|
Hyderabad

02 Sep

ACL Digital

Hyderabad

Job Description
Job Title: RTL Design Engineers
nExp Level: 4+ yrs
nLoctaion: Hyderabad /Bangalore
nJob Description:
n
- n
- RTL coding knowledgen
- Top-level (SOC) level basic industry standard Arch knowledgen
- SoC & IP level Integration knowledgen
- IPXACT knowledgen
- IORING and Phys & GPIOs basic functionalityn
- Design Partitioning(Tilification) knowledgen
- Design RTL quality checks:n
- Clock domain crossing(CDC)n
- Reset domain crossing(RDC)n
- LINTn
- VSIn
- UPF knowledgen
- LEC(Logic equivalence check)n
- Timing concepts & SDC knowledgen

n• Tools knowledge:
n
- n
- Vc_static or equivalent other tools(VSI)n
- VC_spyglass LINT, CDC and RDCn
- 0inn
- Formality and conformal LEC tooln

n• Design and scripting languages:
n
- n
- Verilog and SVn
- Perln
- Pythonn
- TCLn

📌 RTL Design Engineer (Hyderabad)
🏢 ACL Digital
📍 Hyderabad

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