Hiring: Synthesis Engineer | 5+ Years

Location:

Bengaluru
Experience:

5+ Years
⏳

Notice Period:

0–30 Days
Education:

B.E./B.Tech/M.E./M.Tech in ECE, EEE, VLSI, or related disciplines

Job Description:
We are looking for an experienced

Synthesis Engineer

with strong expertise in RTL-to-gate synthesis, logic optimization, timing closure, and PPA optimization for complex ASIC/SoC designs.

Key Responsibilities:
Perform

RTL-to-Gate Synthesis

for complex SoC designs.
Develop and validate

synthesis constraints and SDC .
Perform

logic optimization for Power, Performance and Area (PPA) .
Analyze and resolve

timing, area and power issues .
Work on

multi-clock and multi-mode designs .
Perform

Design-for-Test (DFT) aware synthesis .
Support

timing closure

in collaboration with STA and Physical Design teams.
Debug synthesis issues related to

RTL, constraints and libraries .
Perform

formal equivalence checks

between RTL and synthesized netlist.
Support

Physical Synthesis and implementation-aware optimization .




Analyze synthesis reports and identify optimization opportunities.
Develop and maintain

Tcl-based automation scripts .
Collaborate with

RTL, STA, PD, DFT and Verification teams .

Required Skills:
Strong experience in

Logic / RTL Synthesis .
Hands-on experience with

Cadence Genus / Synopsys Design Compiler / Fusion Compiler .
Strong knowledge of

SDC, timing constraints and synthesis methodologies .
Experience with

multi-clock and hierarchical designs .
Strong understanding of

timing, area and power optimization .
Knowledge of

UPF / low-power synthesis

is an added advantage.
Experience with

Formal Verification / LEC .
Good

Tcl scripting

skills.
Python knowledge is a plus.

Preferred:
Experience with

advanced technology nodes .
Experience in

multi-million gate SoC designs .
Exposure to

physical synthesis and timing-driven optimization .
Robust understanding of the complete

RTL-to-GDSII flow .

📌 Synthesis Engineer (Mumbai)
🏢 Leadsoc Technologies
📍 Mumbai