Job SummaryWe are looking for a skilled Physical Design Engineer to support end-to-end ASIC/SoC implementation from netlist/RTL to GDSII . The engineer will be responsible for physical implementation, timing closure, PPA optimization, physical verification, and sign-off while working closely with RTL, synthesis, STA, DFT, and verification teams.Key ResponsibilitiesExecute the complete physical design flow:FloorplanningPower planningPlacementClock Tree Synthesis (CTS)RoutingOptimizationECO implementationPhysical sign-offPerform Static Timing Analysis (STA) and resolve setup, hold, transition, and clock violations.Analyze and optimize timing, power, area, congestion, and signal integrity .Work on MMMC (Multi-Mode Multi-Corner) implementation and timing closure.Develop and review timing constraints, including SDC, clocks, generated clocks, and timing exceptions .Perform physical verification and sign-off activities including DRC, LVS, antenna, EM/IR, and power integrity checks.Debug placement, routing, congestion, timing, and physical-design violations.Collaborate with RTL, synthesis, STA, DFT, power,



and verification teams to achieve project milestones.Support tape-out activities and ensure design quality meets performance, power, area, and reliability targets.Develop and improve implementation flows using Tcl/Python/Perl/Shell scripting .Participate in methodology development and automation initiatives.Required Technical SkillsStrong understanding of ASIC/VLSI Physical Design flow from RTL/Netlist to GDSII .Valuable knowledge of:FloorplanningPlacementCTSRoutingTiming closureECOPhysical verificationPower planningStrong understanding of setup/hold timing and STA .Knowledge of MMMC analysis and timing constraints .Experience with industry-standard EDA tools such as:Cadence InnovusSynopsys ICC2/Fusion CompilerSynopsys PrimeTimeCadence TempusCalibre/ICVScripting knowledge in Tcl, Python, Perl, or Shell .Understanding of DRC, LVS, EM/IR and power integrity is preferred.Exposure to low-power design/UPF and advanced technology nodes is an advantage.EducationB.E./B.Tech/M.E./M.Tech in Electrical Engineering, Electronics & Communication, VLSI, Microelectronics, or a related field .Experience3–6 years: Physical Design Engineer

📌 PD Engineer-Noida (Kanpur)
🏢 Mirafra Technologies
📍 Kanpur