4. DFT: Synopsys Tool:
Key Responsibilities
DFT Architecture & Planning
Define DFT strategy for complex ASIC/SoC designs.
Develop and review DFT specifications and test architecture.
Drive DFT implementation from RTL to Tapeout.
Collaborate with RTL, Physical Design, Verification, and Validation teams.
Ensure compliance with product quality and test coverage requirements.
Scan Insertion & Scan Compression
Implement and validate scan architecture.
Perform scan chain insertion and optimization.
Develop scan stitching methodologies.
Implement scan compression techniques to reduce tester memory and test time.
Debug scan connectivity and chain-related issues.
Responsibilities Include:
Scan Architecture Definition
Scan Stitching
Scan Chain Reordering
Scan Compression
EDT Implementation
Test Logic Verification
ATPG & Pattern Generation
Generate stuck-at, transition, path-delay, bridge, and cell-aware fault patterns.
Achieve targeted fault coverage goals for production devices.
Debug ATPG violations and improve testability.




Optimize pattern count and test execution time.
ATPG Activities
Stuck-at Fault ATPG
Transition Fault ATPG
Cell-Aware ATPG
Path Delay ATPG
Bridging Fault Coverage
Fault Simulation
Pattern Validation
MBIST/LBIST Implementation
Implement memory BIST architecture for embedded memories.
Support Memory Repair and Redundancy Analysis.
Integrate and verify LBIST implementation.
Collaborate with memory compiler and architecture teams.
Expertise Required
MBIST Planning
MBIST Integration
March Algorithms
Memory Repair Flow
BISR/BIRA Concepts
LBIST Flow
JTAG & Boundary Scan
Implement IEEE 1149.1 compliant JTAG architecture.
Integrate TAP Controller and Boundary Scan logic.
Debug JTAG connectivity and verification issues.
Support board-level test requirements.
Required Knowledge
JTAG
Boundary Scan
TAP Controller
IEEE 1149.1
IEEE 1500

📌 Staff Engineer (Hyderabad)
🏢 Cyient
📍 Hyderabad