DFT Lead (Hyderabad)

DFT Lead (Hyderabad)

02 Sep
|
Cyient
|
Hyderabad

02 Sep

Cyient

Hyderabad

DFT with Cadence Tool:
Key Responsibilities
DFT Architecture & Planning
Define and develop DFT strategy for complex ASIC and SoC designs.
Create DFT specifications and test architecture documents.
Drive DFT implementation activities from RTL through tapeout.
Collaborate with RTL, Design Verification, Physical Design, STA, and Silicon Validation teams.
Ensure high fault coverage while meeting PPA requirements.
Participate in architecture reviews and DFT signoff activities.
Scan Insertion & Test Compression
Design and implement scan architecture.
Perform scan chain insertion and optimization.
Implement scan compression methodologies.
Analyze and debug scan chain violations.
Support scan-chain reordering and physical-aware DFT implementation.
Optimize test time and tester memory utilization.
Key Areas
Scan Insertion
Scan Stitching
Scan Partitioning
Test Compression
EDT Architecture
Scan Reordering
Scan Verification
ATPG & Fault Coverage
Generate ATPG patterns for production testing.
Achieve targeted fault coverage goals.
Perform fault simulation and coverage analysis.




Debug ATPG violations and improve testability.
Optimize pattern count and tester efficiency.
ATPG Activities
Stuck-at ATPG
Transition ATPG
Path Delay ATPG
Cell-Aware ATPG
Bridging Fault Analysis
Fault Grading
Fault Simulation
Pattern Debugging
MBIST Implementation
Develop and integrate MBIST architecture for embedded memories.
Support memory repair and redundancy management.
Implement memory diagnosis and repair solutions.
Verify MBIST functionality and coverage.
Expertise Required
MBIST Architecture
BISR
BIRA
Memory Repair Flows
Memory Diagnosis
March Algorithms
Embedded Memory Testing
JTAG & Boundary Scan
Implement and verify JTAG architecture.
Integrate TAP controllers and boundary scan logic.
Support chip-level connectivity testing.
Debug JTAG and boundary scan issues.
Standards Knowledge
IEEE 1149.1
IEEE 1500
Boundary Scan Architecture
TAP Controller Implementation
DFT Verification
Develop DFT verifi

📌 DFT Lead (Hyderabad)
🏢 Cyient
📍 Hyderabad

Reply to this offer

Impress this employer describing Your skills and abilities, fill out the form below and leave Your personal touch in the presentation letter.

Subscribe to this job alert:

Get the latest job offers by email for: dft lead (hyderabad) / hyderabad