Key Responsibilities
Static Timing Analysis & Signoff
Perform block-level and full-chip timing analysis and signoff.
Drive timing closure across all functional and test modes.
Analyze and fix setup, hold, recovery, removal, transition, capacitance, and pulse-width violations.
Perform timing signoff across multiple process, voltage, and temperature corners.
Execute MCMM (Multi-Corner Multi-Mode) timing analysis and closure.
Validate timing across hierarchical and flat SoC designs.
Timing Closure
Drive setup and hold optimization throughout implementation cycles.
Work closely with Physical Design teams to achieve timing convergence.
Perform timing ECO generation and validation.
Analyze critical timing paths and propose optimization strategies.
Resolve timing bottlenecks while maintaining area and power targets.
Support late-stage tapeout closure activities.
Cadence Signoff Flow
Robust hands-on experience in:
Cadence Tempus Timing Signoff
Cadence Innovus Timing Analysis
Cadence Voltus Integration
Cadence Quantus Extraction
Cadence Conformal ECO
Cadence Genus Synthesis (preferred)
Signal Integrity & Noise Analysis
Perform Crosstalk Analysis.
Analyze and resolve SI-related timing issues.
Validate noise, glitches, and signal integrity effects.
Work closely with physical design teams on route optimization and shielding techniques.
Ensure timing robustness under SI effects.
Low Power Verification
Verify clock gating implementations.
Analyze UPF/CPF constraints.
Validate low-power modes and timing requirements.
Support power-aware timing signoff methodology.
ECO Implementation & Verification
Generate timing ECOs for setup and hold closure.
Work with implementation teams to validate ECO impact.
Perform incremental timing signoff after ECO implementation.
Ensure clean final signoff before tapeout.
Cross-Functional Collaboration
Collaborate with:
RTL Design Teams
Physical Design Teams
DFT Engineers
Verification Teams
Architecture Teams
Foundry Support Teams
Participate in desig