02 Sep
|
MediaTek
|
Bengaluru
02 Sep
MediaTek
Bengaluru
GHz range)Analyzing the timing reports and identifying both design and constraints related issues. Worked on blocks with multiple power and voltage domains Preferred EDA tool experience: Primetime, Tweaker/Prime Closure, Innovus Strong Understanding of DFT modes requirements for timing signoff Valuable understanding of physical design flow and ECO implementation Strong understanding of SDC constraints, OCV, AOCV, POCV analysis Strong TCL/scripting knowledge is mandatory. ACADEMIC CREDENTIALS: Bachelors or Masters degree in Electrical Engineering
📌 Sta Engineer (Bengaluru)
🏢 MediaTek
📍 Bengaluru