We have an opening for FPGA Design engineer role - Bangalore
/n
/n
REQUIRED:
/n
/n
EXP: 5 to 12 years
/n
/n
- Experience with FPGA system design from IP Integration to implementation, Verilog RTL based IP design, Verilog/System Verilog based testbench development
/n
- Experience with AMD Vivado & Vitis SDK & VItis AI tools.
/n
- Experience with C/C++ in developing Embedded FW & scripting automation using Python
/n
- Experience with Petalinux build flow , familiarity with Uboot, linux driver changes and FPGA SoC debugging.
/n