Responsibilities
Robust ASIC RTL design (Verilog/SystemVerilog), CDC, Lint.
Experience in micro-architecture, integration, and debugging.
Exposure to synthesis, timing, and low-power design.
Team leadership and cross-functional collaboration skills.
Qualifications
Bachelors or Master s degree in Electrical Engineering, Computer Engineering, or a related field.
Disclaimer: This job posting has been aggregated from external source. Role details, content, and availability are subject to change. Applicants are advised to confirm the latest information directly on the company website before applying.
📌 Asic Rtl Design Lead Verilog/systemverilog, Cdc, Lint Id 014 Noida
🏢 Vitestork Consulting
📍 Noida
Reply to this offer
Impress this employer describing Your skills and abilities, fill out the form below and leave Your personal touch in the presentation letter.