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At AMD, we believe technology can change lives for the better. It can heal us, entertain us, and make us more connected, productive, and understanding of the world around us. And we’re looking for talent who feel the same: people who want to leave the planet better than they found it, those who don’t shy away from humanity’s challenges but are determined to help solve them.
AMD is powering the next generation of supercomputing, high-performance computing, cloud, and AI. Whether you’re designing next-gen processors, enabling AI breakthroughs, or creating go-to-market plans, every role at AMD contributes to something bigger — technology that moves the world forward.

MTS SILICON DESIGN ENGINEER (STA/Timing)
KEY RESPONSIBILITIES:
Responsible for the development of complex multi-mode / multi-corner timing constraints that are compatible for RTL and signoff
Ensuring constraints quality (SDC) using industry tools like Fishtail , GCA
Well versed with timing signoff methodology and corner definitions




Drive the pre-route timing checks and QoR clean up to eliminate SDC issues and ensure a quality handoff for STA checks
Requires a mix of SDC knowledge, EDA timing tool competence and Tcl based scripting capability (in both EDA workplace and standalone Linux Tcl shell scripts)
Responsible for Timing closure of one or multiple sub chip/subsystem OR Full chip.
Ensuring full chip level Interface timing closure along DRV closure
Generating timing ECO using tools DMSA/Tweaker and leading subsystem/Subchip/FC timing closure
PREFERRED EXPERIENCE:
8+ years of experience in building the timing constraints for IPs, blocks and Full-chip implementation in both flat/hierarchical flows.
Experience with analyzing the timing reports and identifying both the design and constraints related issues.
Preferred EDA tool experience: Synopsys Design Compiler/Primetime, Spyglass, Fishtail, Tweaker etc.
Experience in timing closure of high frequency blocks & subs

📌 STA Silicon Design Engineer (Bengaluru)
🏢 Advanced Micro Devices
📍 Bengaluru