Design Verification Engineer
Experience : 1–3 years
Location : Bangalore
The Role: Debug core/subsystem simulation/emulation failures across pipelines (Fetch/Decode, Execution, Floating Point, Cache) and enhance automated triage tools using Python/C++.
Key Specs: Robust computer architecture background (x86/ARM), assembly/C++ verification, SystemVerilog/UVM, and scripting experience.
Bonus Points: Exposure to post-silicon debug, ML/AI-driven verification techniques, and processor microarchitecture.
Apply: Send your resume to
[email protected] to drive next-gen silicon quality
📌 Design Verification Engineer (Bengaluru)
🏢 ACL Digital
📍 Bengaluru