Job DescriptionLEAD BEHAVIORAL MODELING ENGINEER – LATTICE SEMICONDUCTOR INDIA N Location: Hyderabad / Pune / Chennai (India) NJOB SUMMARYnWe are seeking a Lead Behavioral Modeling Engineer to join Lattice Semiconductor's FPGA Architecture & Design team. You will lead development of behavioral and architecture models for next-generation low-power FPGA fabrics, own power and timing characterization, and mentor a small modeling team. NThis is a technical leadership role focused on modeling methodology and design optimization—not traditional product RTL design or verification. NKEY RESPONSIBILITIESn N Develop and maintain behavioral models for FPGA fabric elements (CLBs, routing, interconnects, logic blocks) N Own power and timing characterization across PVT (Process, Voltage, Temperature) corners N Build Python-based automation flows for rapid design exploration and PPA analysis N Lead modeling methodology improvements and drive continuous optimization N Collaborate with architecture, RTL, and circuit design teams to validate design intent N Mentor and guide modeling engineers on best practices and technical excellence N Correlate behavioral models against silicon measurements and real chip data N Establish and communicate modeling standards and documentation NnREQUIRED QUALIFICATIONS Nn Bachelor's degreein Electrical Engineering or related field (Master's preferred) N 8+ years in behavioral/architecture modeling or FPGA/ASIC design N 2+ years of technical leadership experience N Proficiency in C++, SystemC,



and Python for model development N Deep knowledge of FPGA fabric architecture (CLBs, LUTs, routing, interconnects) N Robust understanding ofpower and timing characterization methodologies N Excellent problem-solving and technical communication skills N Ability to lead cross-functional teams and drive collaborative efforts NnPREFERRED QUALIFICATIONS Nn Master's degree (M.Tech, MS) in Electrical/Computer Engineering N Prior experience at semiconductor companies N Published papers or patents in FPGA modeling or architecture optimization N Experience with ML-based power prediction or on-die sensor integration N Test-chip bring-up and silicon validation experience NnWHAT YOU WILL NOT BE DOING NThis role is NOT focused on: Nn Verilog/VHDL/SystemVerilog code development for product design N SystemVerilog testbenchand formal verification N Gate-level or post-layout simulation N Traditional Design Verification (DV) N Physical design (place & route, floorplanning) NnIf your backgroundis primarily RTL design or DV, this may not be the right fit. NWHY LATTICE SEMICONDUCTOR? NLattice is the global leader in low-power FPGA solutions for edge AI, automotive, aerospace, and IoT. Your modeling work directly impacts next-generation FPGA architectures and time-to-market for innovative products. NWe offer: Nn Deep technical challenge and leadership opportunity N Collaborative, innovation-driven culture N High-impact products used globally N Competitive compensation and benefits N

📌 Lead Behavioral Modeling Engineer - Lattice Semiconductor India (Hyderabad)
🏢 Lattice Semiconductor
📍 Hyderabad