Job Description Static Timing Analysis (STA) Engineer N Experience: 3 to 6 years of experience in STA. N Location:- Bangalore N Job Summary nThe Static Timing Analysis (STA) Engineer will own the timing sign-off and closure for complex integrated circuits (ICs) and/or System-on-Chips (SoCs). This role involves defining and validating timing constraints, performing multi-mode multi-corner (MMMC) timing analysis, and collaborating with design and physical design teams to achieve the target operating frequency and performance metrics. N Key Responsibilities Nn Timing Sign-off and Analysis N Timing Closure Ownership: Drive all aspects of timing closure from pre-layout to post-layout for blocks, sub-systems, and/or the full chip. N Constraint Management: Develop, validate, and maintain Synopsys Design Constraints (SDC) and timing constraints for all functional and test modes (e.G., Scan, MBIST). N MMMC Analysis: Perform comprehensive timing analysis across multiple operating corners (Process, Voltage, Temperature - PVT) and various modes (Multi-Mode Multi-Corner). N Critical Path Identification:



Analyze timing reports to identify and debug critical paths and resolve all Setup and Hold violations. N Signal Integrity (SI) &Noise;: Incorporate advanced timing effects such as on-chip variation (OCV), signal integrity (crosstalk), and voltage drop (IR-drop aware STA) into the sign-off process. Nn Methodology and Flow Nn Develop, maintain, and enhance STA flows and methodologies to improve efficiency, robustness, and reduce analysis runtime. N Automate repetitive tasks and report generation using scripting languages. N Generate final timing reports and sign-off collateral for tape-out. Nn Education Nn Bachelor's or Master's degree in Electrical Engineering (EE), Electronics Engineering, VLSI, or a related field. Nn Technical Skills Nn EDA Tools: Expert proficiency with industry-standard Electronic Design Automation (EDA) tools from vendors like Synopsys (e.G., Fusion Compiler, ICC2, Primetime), Cadence (e.G., Innovus), or Mentor Graphics. Nn

📌 Senior Static Timing Analysis (Sta) Engineer (Bengaluru)
🏢 Leadsoc Technologies
📍 Bengaluru