Job Description

Renesas India is seeking an experienced Senior Staff Physical Design Engineer to lead subsystem- and block-level physical implementation and closure for complex hierarchical SoCs at advanced technology nodes. This role requires deep expertise in timing, congestion, power integrity, and clocking methodologies, along with solid cross-functional collaboration skills. While this role does not own SoC-level physical design, it plays a critical role in aligning subsystem implementation with overarching SoC strategies.

Key Responsibilities

- Lead block- and subsystem-level physical design closure, including timing closure, congestion mitigation, power integrity, and overall physical implementation quality
- Collaborate closely with SoC-level physical design teams to align on clocking strategies, floorplanning intent, and integration requirements, without direct ownership of SoC-level execution




- Apply deep understanding of clocking methodologies to ensure subsystem-level clock domains integrate cleanly into the broader SoC clock architecture
- Develop, refine, and scale subsystem closure methodologies, flows, and automation, improving predictability, quality, and execution efficiency
- Mentor and guide physical design engineers within subsystem teams, promoting best practices, technical rigor, and methodology adoption
- Work cross-functionally with RTL design, STA, power, verification, and backend teams to ensure smooth handoffs and robust closure
- Proactively identify, assess, and mitigate physical design risks, coordinating closely with SoC teams to manage impacts and drive solution.

📌 Staff Engineer, Physical Design (Bengaluru)
🏢 renesas electronics
📍 Bengaluru