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Experience: 6+ yrs

Location: Bengaluru

Job Type: Full time

We are seeking a highly skilled
Senior Emulation / Pre-Silicon Validation Engineer
to support pre-silicon validation for complex ASIC and SoC designs using advanced hardware emulation platforms. This role is ideal for professionals with deep expertise in Cadence Palladium environments, hardware/software co-validation, and SoC debugging who are passionate about accelerating silicon validation and improving product quality before tape-out.

As a Senior Emulation / Pre-Silicon Validation Engineer, you will collaborate closely with RTL, Verification, Firmware, Architecture, and Software teams to build scalable emulation environments, enable efficient hardware/software integration, and validate complex SoC functionality. You will play a key role in optimizing emulation workflows, debugging functional issues, developing transactors, and ensuring robust pre-silicon validation across multiple subsystems.

Requirements




Key Responsibilities
- Develop, maintain, and optimize hardware emulation environments using Cadence Palladium platforms
- Support Palladium build, compilation, partitioning, clocking, and debug flows for large-scale ASIC and SoC designs
- Design and develop SystemC/C++ transactors, reference models, and validation infrastructure
- Enable and support ICE (In-Circuit Emulation) and Virtual Interface (VIF)-based validation environments
- Perform hardware/software co-validation by integrating firmware and software with emulated hardware platforms
- Debug functional, integration, and performance issues across hardware and software components
- Collaborate with RTL, Verification, Firmware, and Architecture teams to accelerate validation and issue resolution
- Develop automation scripts using Python, TCL, Perl, or Shell to improve validation efficiency and regression execution
- Analyze validation resu

📌 Senior Emulation (Bengaluru)
🏢 Weekday AI (YC W21)
📍 Bengaluru