Develop RTL for Cores related to security and Security Sub System.
Running ASIC development tools including Lint, CDC, Low power checks.
Report status and communicate progress against expectations.
3 to 5 + years of Hardware Engineering experience or related work experience.
Preferred Qualifications-
• Min 3 to 5 years of work experience in ASIC/SoC Design
• Experienced in RTL design using Verilog / System Verilog.
• Knowledge of cryptography algorithms is a plus
• Experienced in Linting, CDC and LEC.
• Experienced in database management flows with Clearcase/Clearquest.
• Ability to program effectively in Verilog, C/C++, Python, Perl
• Excellent oral and written communications skills
• Proactive, creative, curious, motivated to learn and contribute with positive collaboration skills..