We are looking for an experienced Senior RTL Design Engineer with 7+ years of experience in digital logic design and hands-on RTL coding using Verilog/SystemVerilog. The ideal candidate should have solid expertise in digital design, RTL development, design quality, timing, and ASIC/SoC development.
Required Skills
- 7+ years of experience in digital logic design and RTL development.
- Strong hands-on experience with Verilog and SystemVerilog.
- Strong understanding of control-path and data-path design concepts.
- Experience with RTL design methodologies and correct-by-construction design principles.
- Experience defining DV requirements, test plans, and coverage metrics.
- Knowledge of
- Lint
- CDC
- Formal Equivalence
- DFT concepts
- Power analysis
- Logic Synthesis
- Static Timing Analysis (STA)
- Timing constraints
- Strong debugging, analytical, and problem-solving skills.
- Excellent communication and teamwork skills with the ability to work with globally distributed teams.
Good to Have
- Experience with standard on-chip protocols such as APB, AHB, AXI, and AXI-Stream.
- Knowledge of Processor/SoC architecture.
- Understanding of DSP fundamentals.
- Experience with complete ASIC/SoC product development and productization.
- Exposure to front-end RTL-to-GDSII design flow is an added advantage.
Interested can share resume on
[email protected]
📌 Senior/Lead Digital Design Engineer (Bengaluru)
🏢 incise infotech
📍 Bengaluru