PD_ Analog Design Engineer (Pune)

PD_ Analog Design Engineer (Pune)

02 Sep
|
Arrow Ec
|
Pune

02 Sep

Arrow Ec

Pune

Position:

RTL2PD_ Analog Design Engineer

:

JD

5 to 8 years of experience in RTL Synthesis, Timing Constraints / SDC checking / reviewing / small fixes / finding errors etc. Should have done at least 3 ASIC projects. CDC, Lint clean up and automation with scripts.

Timing

Report analysis, Static Timing Analysis Tools : Genus / FC : Synthesis, Optimization or DC compiler, DCTopo Spyglass : Constraints checking / CDC Checking LEC / Formality : Formal Verification, VCLP.

Primetime : Zero delay Timing analysis.

Location:

IN-MH-Pune, India-Blue Ridge-Hinjewadi (eInfochips)

Time Type:

Full time

Job Category:

Engineering Services

📌 PD_ Analog Design Engineer (Pune)
🏢 Arrow Ec
📍 Pune

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