Physical Design Engineer 5 to 10 Years

:

We are looking for experienced Physical Design Engineers with 5–10 years of experience in end-to-end RTL-to-GDSII implementation for advanced semiconductor designs.

Key Responsibilities:

- Perform Netlist to GDSII / RTL-to-GDSII implementation.
- Handle Floorplanning, Power Planning, Placement, CTS, Routing, and Physical Verification.
- Perform Timing analysis and optimization including setup/hold closure.
- Work on Physical Design closure for PPA, timing, congestion, and power.
- Handle ECO implementation and timing/area optimization.
- Analyze and resolve DRC, LVS, antenna, IR/EM and other physical design issues.
- Work closely with STA, RTL, DFT, PV, and Synthesis teams for design closure.
- Experience with advanced technology nodes and high-performance designs is preferred.




- Automate/optimize PD flows using TCL, Python, or Perl.

Required Skills:

- Strong understanding of Physical Design flow and methodologies.
- Hands-on experience with ICC2 / Fusion Compiler / Innovus.
- Good knowledge of PrimeTime / Tempus for timing analysis.
- Experience with UPF/Low Power concepts is an added advantage.
- Solid debugging and problem-solving skills.
- Experience in block-level and/or full-chip implementation.

Experience: 5–10 Years

Location: Bangalore

Notice Period: Immediate to 30 Days preferred

Interested candidates can share their updated resume at:

[email protected] & responsibilities

📌 Physical Design Engineer (Bengaluru)
🏢 Mirafra
📍 Bengaluru