Department: Front End Engineering

Reports To: BU Head

Location: Bengaluru

Employment Type: Full Time

Job Summary The RTL Integration Engineer will be responsible for the integration of third-party ASA IP into the Camera

Serializer digital subsystem. The role requires strong expertise in RTL integration, digital design, clock-domain crossing, interface adaptation, register and CSR methodology, and integration of digital and Analog/Mixed-Signal

IP blocks.

The engineer will work closely with Design, Architecture, PHY, Verification, and Analog/Mixed-Signal teams to ensure that integrated IPs meet functional, timing, connectivity, quality, and safety requirements. The role will involve ownership of IP integration activities from specification understanding through RTL implementation,

analysis, lint/CDC closure, subsystem integration, and final sign-off.

Key Skills &

- Responsibilities
- Authoring and owning 3rd party IP integration

Own the end-to-end integration of third-party IPs into the target digital subsystem. This includes understanding IP specifications and interfaces, defining integration requirements, establishing connectivity between IP blocks,

resolving interface dependencies, and ensuring that the integrated IP functions correctly within the overall subsystem architecture. The candidate should be comfortable taking ownership of integration issues and working with IP vendors, architects, designers, and verification teams to resolve technical dependencies and integration challenges.

- ASA-ML-T-22ULL PHY integration

Hands-on experience with ASA-ML-T-22ULL PHY integration is required. The candidate should be able to understand the PHY interface and associated specifications and successfully integrate the PHY with the surrounding digital logic.

Responsibilities include managing digital-side connectivity, interface requirements,

configuration and control paths, and ensuring correct interaction between the PHY and the Camera Serializer digital subsystem.

- Multi-domain CDC analysis

Perform Clock Domain Crossing (CDC) analysis across multiple clock domains within the subsystem.



The candidate should understand asynchronous clock-domain interactions, identify potential CDC violations, and work on appropriate synchronization and data-transfer mechanisms. The role involves analyzing CDC reports,

debugging violations, coordinating with RTL/design teams, and driving CDC closure while maintaining functional correctness and reliability of the integrated design.

- ASEP 8-port interface: 32-to-16-bit width adaptation, async FIFO design, STYPE routing, SOP/EOP framing

Work on the ASEP 8-port interface, including 32-to-16-bit width adaptation, asynchronous FIFO design, STYPE routing, and SOP/EOP framing. The candidate should be capable of designing and integrating the required RTL logic for data-width conversion and asynchronous data movement while ensuring correct packet/frame handling.

The engineer will ensure that Start-of-Packet (SOP) and End-of-Packet (EOP) information is preserved correctly and STYPE-based routing operates according to the relevant specification.

- APB/SOC slave bus bridge; register map ownership
- RGGEN-based CSR methodology

Own the design and integration of the APB/SoC slave bus bridge, including responsibility for the associated register map. The candidate should have experience defining and implementing register interfaces, understanding address maps, handling read/write transactions, and ensuring correct connectivity between the SoC bus and integrated IP.

Experience with RGGEN-based CSR methodology is required, including structured approaches for generating and managing Control and Status Registers (CSRs).

- SystemVerilog (RTL and assertions), lint, linting closure, Cadence CDC tool

Strong hands-on experience with SystemVerilog for RTL development and assertions. The candidate should be capable of writing clean,



synthesizable RTL and using assertions to capture design intent and verify key functional properties.

Experience with Cadence HAL/SpyGlass linting, linting closure, and Cadence CDC tools is required. The candidate should be comfortable analyzing reports, implementing fixes, and driving closure.

- Working knowledge of ASA-ML DLL, PCS, OAM, PTB, and ASEP layers
- PHY datasheet/spec fluency

Working knowledge of the ASA-ML DLL, PCS, OAM, PTB, and ASEP layers is expected. The candidate should be comfortable reading and interpreting PHY datasheets and specifications, understanding interface behavior, and translating protocol and PHY requirements into practical RTL integration activities.

- Co-simulations between Digital and Analog/Mixed-Signal IP blocks

Experience with co-simulation between Digital and Analog/Mixed-Signal IP blocks. The candidate should understand the challenges involved in integrating digital logic with AMS components and participate in co-simulation activities to validate interactions between digital and analog/mixed-signal portions of the design.

- MBIST/LBIST and redundancy

Experience or working knowledge of MBIST, LBIST, and redundancy mechanisms as part of the overall chip integration and test strategy. The candidate should understand how memory and logic test mechanisms are incorporated into the SoC and how these mechanisms interact with the overall digital architecture.

- Safety mechanism to make whole chip compliant to FuSa requirements

Work on the integration and implementation of safety mechanisms required to make the whole chip compliant with Functional Safety (FuSa) requirements. The candidate should understand how safety requirements translate into hardware design and integration requirements and collaborate with architecture, design, verification,

and safety teams to ensure required mechanisms are correctly implemented and integrated.

Qualification &

- Experience
- B.E / B.Tech / M.E / M.Tech
- 8 to 12 Years

Salary Range: 45 LPA to 60 LPA

Advantages: As per company policy

Travel Requirements: As per client requirement

📌 Modernize Chip Solutions - RTL Integration Engineer (India)
🏢 Modernize Chip Solutions
📍 India