Hiring: Design Verification Lead & Senior Design Verification Engineer

Location: Bangalore

Experience: 5–15 Years

Notice Period: 0–30 Days

Key Skills & Domain Expertise

We are looking for experienced Design Verification professionals with expertise in one or more of the following:

- High-Speed Protocols
- PCIe
- UCIe
- DDR
- Ethernet
- CPU Verification
- GPU Verification
- GLS (Gate-Level Simulation)
- RISC / RISC-V
- ARM Cortex

Roles & Responsibilities
- Develop and execute verification plans for IP, Subsystem, and SoC-level designs.
- Build and maintain robust SystemVerilog and UVM-based verification environments.
- Develop testbenches, sequences, test cases, and reusable verification components.
- Perform functional verification, assertion-based verification, and coverage closure.
- Debug complex simulation failures and collaborate with RTL, architecture, and design teams.




- Drive verification from planning through execution and final sign-off.

Required Skills
- Solid hands-on experience in SystemVerilog and UVM.
- Experience in IP, Subsystem, or SoC Verification.
- Expertise in one or more of the listed domains/protocols.
- Strong knowledge of functional coverage, code coverage, assertions, and debugging.
- Knowledge of Python, Perl, or Shell scripting is an added advantage.

Additional Requirements for Design Verification Lead
- Lead and drive end-to-end verification activities.
- Define verification strategies and plans.
- Drive coverage closure and resolve complex verification challenges.
- Mentor and guide team members.

Interested candidates can share their profiles at: [email protected]

📌 Senior/ Lead Design Verification Engineer (Bengaluru)
🏢 Leadsoc Technologies
📍 Bengaluru