Role Overview

The focus of this role is to plan, build, and execute the design and validation of new and existing features for AMD's DDR IPs and custom IPs. Collaborate with cross-functional teams to design and integrate DDR memory controller calibration solutions, including RTL logic, firmware routines, and algorithmic flows, into AMD's system-level validation and bring-up environments. Ensure seamless interaction between hardware and firmware components, delivering reliable calibration performance aligned with silicon and platform requirements. To work on custom IP projects.

Responsibilities

- Design and implement robust firmware solutions for DDR memory controller calibration across various DDR standards

- Develop and refine calibration algorithms to ensure reliable memory initialization and operation under varying process, voltage, and temperature (PVT) conditions. Focus on improving accuracy, convergence speed, and adaptability of calibration routines

- Create and execute validation plans to verify the correctness and performance of calibration firmware, algorithms and custom IPs. Perform system-level bring-up and debug activities to identify and resolve issues related to memory training and stability

- Work closely with silicon design, verification, and system engineering teams to align calibration firmware with hardware capabilities and system requirements. Ensure seamless integration and interoperability across the full memory subsystem

- Stay updated with emerging DDR technologies and calibration techniques.



Propose and implement creative solutions to improve calibration robustness, reduce boot time, and support next-generation memory interfaces

Preferred Experience

- B.E/M.E/M.Tech or B.S/M.S in EE/CE with 9+ years of relevant experience

- Digital design and experience with RTL design in Verilog/SystemVerilog, Knowledge of system-level architecture including buses like AXI/AHB, bridges

- Circuit timing/STA, and practical experience with tools

- Working knowledge of C; embedded experience a plus

- Understanding of memory technologies such as DDR4, DDR5, LPDDR, and JEDEC standards

- Been exposed to memory controller and PHYs from different IP vendors

- Experienced with implementing DRAM/memory controller initialization code, memory subsystem/DDR PHYs training/calibration software

- Version control systems such as Perforce, ICManage or Git

- Familiar with industry standard lab tools (such as: high speed scope, compliance packages, logic analyzers) is a plus

- Strong verbal and written communication skills

- Should have experience working in geographically dispersed team and should be a strong team player

Academic Credentials

- Bachelors or Masters degree in computer engineering/Electrical Engineering with 12+ yrs of exp

Disclaimer: This job posting has been aggregated from external source. Role details, content, and availability are subject to change. Applicants are advised to confirm the latest information directly on the company website before applying.

📌 Lead RTL Design & Validation Engineer with DDR protocols exp (Hyderabad)
🏢 Advanced Micro Devices (AMD)
📍 Hyderabad